Cadence announced a transformative step forward in redefining how semiconductors are designed with the launch of the ChipStack AI Super Agent—an agentic AI solution for front-end silicon design and verification.
The Cadence ChipStack AI Super Agent is the world’s first agentic workflow for automating chip design and verification. It provides up to 10X productivity improvements for coding designs and testbenches, creating test plans, orchestrating regression testing, debugging
and automatically fixing issues. San Jose, California-based Cadence is one of Silicon Valley’s stalwart companies — not so famous itself but enabling massive chip companies to design their chips, which are the backbone of all electronics and could exceed $1 trillion in revenues by 2030.
“ChipStack represents a major leap in our design-for-AI and AI-for-design strategy, applying agentic AI directly to our customers’ front-end flows to tackle the growing complexity and scale of modern chips,” said Anirudh Devgan, president and CEO of Cadence, in a statement. “By leveraging intelligent agents that autonomously call our underlying tools, we are enabling dramatic productivity gains for our customers in critical design and verification tasks while freeing scarce engineering talent to focus on innovation.”
The newly launched ChipStack AI Super Agent exemplifies Cadence’s approach to Intelligent System Design, where AI orchestration, principled simulation and accelerated computing work seamlessly together to deliver transformative solutions for semiconductor and system innovation.
This agentic AI solution orchestrates multiple virtual engineers, all using Cadence’s foundational EDA tools. The technology integrates agentic AI with proven Cadence optimization AI and AI assistant solutions, which have been used in over 1,000 tapeouts to date, including the Verisium Verification Platform and Cadence Cerebrus Intelligent Chip Explorer, as well as Cadence’s JedAI data and AI platform.
The ChipStack AI Super Agent flexibly supports cloud-based and on-premises frontier models, including Nvidia NeMo framework and Nvidia Nemotron open models and cloud-hosted models such as OpenAI GPT, to improve designer productivity. This continues the fulfillment of the vision of a true “silicon agent,” spanning the many disciplines and workflows needed to deliver the next generation of intelligent devices.
“Our customers are facing a significant senior deficit in the engineering talent needed to deliver on their product roadmaps,” said Paul Cunningham, vice president and general manager of Research and Development, Cadence, in a statement. “Our ChipStack AI Super Agent is a game changer for design and verification productivity, and deployments are ramping fast.”
The Cadence ChipStack AI Super Agent is in early deployment with several of the world’s top chip design and system companies, including Altera, Nvidia and Tenstorrent, among others.
“The Cadence ChipStack AI Super Agent has significantly reduced our verification effort in
some areas by approximately 10X, enabling our team to achieve closure much more swiftly and confidently,” stated Arvind Vidyarthi, senior director of engineering, Altera, in a statement. “By pairing an interactive, engineer-in-the-loop experience with Cadence’s advanced AI-driven verification technologies, we are realizing step-function productivity gains and achieving deeper functional coverage on our most complex designs.”
“As semiconductor complexity continues to accelerate, AI has become essential to designing the next generation of chips,” said Timothy Costa, GM of Industrial and Computational Engineering, Nvidia, in a statement. “Our collaboration with Cadence, including innovations like the ChipStack AI Super Agent, demonstrates how combining intelligent reasoning capabilities such as Mental Models and automated formal test plan generation with Nvidia accelerated computing can unlock new levels of productivity and efficiency for chip designers.”
“ChipStack greatly improved the efficiency of our formal verification efforts,” said Daniel
Cummings, principal engineer of RISC-V Cores, Tenstorrent, in a statement. “During a three-month evaluation on three critical design blocks, it reduced verification time by up to 4X. Running the agent on Tenstorrent hardware also demonstrated our ability to deliver the high-performance, on-prem inference needed for production-scale LLM workloads.”
The Cadence ChipStack AI Super Agent is available now in early access. For more information, please visit Cadence’s AI for Design product page.
The engineer’s view
Matt Graham, senior group director verification software product management, said in an interview with GamesBeat that there’s a shortage of engineers to design and verify chips to the tune of around 300,000 people.
A 23-year veteran at Cadence, Graham started as chip designer and verification engineer, said that the super agent can help engineers be more productive designing silicon chips and then verifying that the circuits are correct across a complex integrated circuit.
This is a very different way to design chips than folks like Graham encountered in the era of electronic design automation, which is automated software for designing the complex circuitry of chips. EDA software brought huge productivity gains, and Graham thinks an even bigger leap is happening now.
“Over the past decade and a half, maybe even more, we’ve we’ve expanded from just electronic design into system design that started with PCB and 3D IC. Now it’s moved into multi physics — things like computational fluid dynamics and electromagnetics and microwave and even finite element analysis in the mechanical domain all the way through the data center,” Graham said.
He said the base that spans everything from molecular biology to data centers is “our base, or what we call principle simulation and automation optimization engines for developing electronics and now electromechanical systems.
“All of that software has really provided huge productivity gain that has to address the need of these electric ICs and electronic systems over the years and that’s brought in a lot of automation in terms of circuit design, circuit layout and so on,” Graham said. “Of course, to keep up with the demand, we’ve also created our own supercomputers, things like the Palladium to help the productivity of those engines [so they can] meet the demand. But the demand continues to increase.”
All of that is driven by the AI infrastructure build out to support consumer demand for things like ChatGPT from OpenAI.
The AI journey
“About six years ago, we started down the path of AI, initially with machine learning and reinforcement learning, to just optimize those fundamental engines, and now today, into agentic AI with this announcement of the ChipStack AI Super Agent, which is turning from just optimizing the engines, things like simulation and an implementation, to actually automating the the IP, the intellectual property creation.”
He said it is literally using AI to create circuits and create intellectual property. It’s also being used to test devices.
“It’s the first step towards full autonomous systems,” Graham said. “Or the next step toward autonomous IC design.”
Not replacing engineers. Making them more productive
The idea is not to replace human engineers altogether.
“One of the key pieces is that it’s the seamless integration of AI and the fundamental tools. So we’re not replacing any of our digital logic simulation and our arithmetic engines, our our debug capability. We’re not replacing any of the fundamental tools that we have provided to IC design customers for four decades now,” Graham said. “We’re integrating them. Those are still fundamentally required. We’re integrating them with AI in the front end of that process to start to generate the actual source code that constitutes the circuit design.”
What’s the payoff? It’s not tech for the sake of technology.
“It’s all about the productivity gap. Complexity continues to increase in the in the circuits themselves, in the ICS, and then the total semiconductor industry, of course, is continuing to grow with probably the forecast for for where it’s going to be in 2030 is probably doubled over the last two or three years up to greater than $1 trillion dollars,” Graham said.
Graham said, “And to meet that demand, to do engineering and and design, we’re estimating somewhere around 300,000 engineering jobs unfilled. And so it’s not about the talent of the individual engineers. It’s just the raw pool of talent is not growing fast enough to meet the demand. And so this is where AI can come in to start to fill that gap.”
He said Cadence has to go from enhancing the tools to providing virtual engineers that are going to fill that productivity gap.
“Engineers don’t need to worry about being replaced by AI. There’s this huge productivity gap, but they’re going to need to use AI, obviously, to enhance their own productivity just to meet the demand,” Graham said.
For about five years, Cadence has been deploying these optimization AI tools that have focused on things like power, performance and area of silicon. The quality of results and the usage of our tools or decreased turnaround time, increased performance for fundamental engines, he said.
Cadence has deployed the super agent with about 10 customers.
“We’re seeing up to 10 times productivity boost and actually even more, in some cases, for tasks like coding designs and test benches, creating test plans for those designs, orchestrating regression testing around those designs, integrating multiple IPS together into SoCs and debugging and auto fixing when problems arise,” Graham said.